1. Field of the Invention
The present invention relates to electronic packaging technology and more generally, to a wafer level stack structure in a system-in-package and method thereof.
2. Description of the Related Art
An electronic package, which may be referred to as a semiconductor package, may be defined as the housing and interconnection of integrated circuits, which may be referred to as the chip or the die, which may form an electronic system. The electronic package may include a structure to physically support the chip, a physical housing to protect the chip from the environment, a means of heat dissipation, and electrical connections to allow signal and power access to and from the chip. Packaging technology may be a factor in the determination of the price, performance, and reliability of a final semiconductor product.
Three-dimensional stack technology is a method of creating semiconductor packages currently used in the art. A chip stack that utilizes three-dimensional stack technology may be fabricated at the chip level by conventional methods. However, a wafer level fabrication technique has been recently developed to achieve simpler, more cost-effective chip stack packages.
The Wafer-Level Chip-Scale Package (WLCSP) is a type of packaging which enables the integrated circuit (IC) to be attached to a circuit board face-down, with the chip's pads connecting to the circuit board's pads through individual solder balls without needing any underfill material. This technology differs from other packaging technologies because there are no bond wires or interposer connections. An advantage of the WLCSP is a reduction of inductance in the electronic device being packaged. Other benefits of the WLCSP may include a reduction in package size, manufacturing cycle time and enhanced thermal conduction characteristics.
System-in-package (SIP) is a technology which may allow integrated single packaging of different kinds of electronic devices. SIP may offer increases in the performance and function of semiconductor devices while decreasing their size and/or cost.
FIG. 1 illustrates a cross-sectional view of a SIP using a chip level stack technique according to conventional methods. Referring to FIG. 1, the SIP 10 may include electronic devices of different sizes illustrated by elements 12, 13 and 14. The elements 12, 13 and 14 are stacked on a common circuit board 11, attached with an adhesive 15, and electrically coupled to the common circuit board 11 with bonding wires 16. An encapsulant 17, such as an epoxy resin, is provided on an upper surface of the board 11 to protect the devices 12, 13, 14 and the wires 16. A plurality of solder balls 18 may be included on a lower surface of the common circuit board 11.
FIG. 2 illustrates a plan view of device chips of the SIP of FIG. 1 according to conventional methods. The device chips 12, 13 and 14 are not typically aligned with each other. Specifically, the number of input/output (I/O) pads 12a, 13a and 14a, etc., may differ from device chip to device chip.
The conventional SIP 10 is currently limited to application at the chip level only. Thus, there is currently no method of applying WLCSP to a SIP.